As among different types of Random Access Memories, there now exists a class of devices know as Dynamic Random Access Memories (DRAM). Such devices, like Static Random Access Memories (SRAM), possess the ability to read and write binary data. However, DRAM can achieve high density due to its structural simplicity. The row and column addresses of DRAM are usually multiplexed on the same address pins.
Designers who implement DRAMs within an electronic circuit often seek to incorporate diagnostic capabilities to automatically verify the operation of the devices in the circuit. In particular, the ability to verify the status of the address pins of a DRAM becomes important. If one of the address pins of the DRAM remain stuck high or low, the device will not operate properly, giving rise to an error.
Present day DRAM verification methods usually do not take the physical pin connections into consideration. Most address verification methods check all of the address space by writing a known data pattern to each location, and then reading the stored pattern from that location for comparison. Checking the physical address space of a DRAM in this manner consumes significant time and does not explicitly verify the address pins of the DRAM.
Thus a need exists for a technique for verifying the address pins of a DRAM.